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240pin Registered DDR2 SDRAM DIMMs based on 2Gb version A
This Hynix Registered Dual In-Line Memory Module (DIMM) series consists of 2Gb version A DDR2 SDRAMs in Fine Ball Grid Array (FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 2Gb version A based Registered DDR2 DIMM series provide a high performance 8 byte interface in 5.25" width form factor of industry standard. It is suitable for easy interchange and addition.
FEATURES
* JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface 8 Bank architecture Posted CAS Programmable CAS Latency 3, 4, 5, 6 OCD (Off-Chip Driver Impedance Adjustment) ODT (On-Die Termination) * * * * * * * * Fully differential clock operations (CK & CK) Programmable Burst Length 4 / 8 with both sequential and interleave mode Auto refresh and self refresh supported 8192 refresh cycles / 64ms Serial presence detect with EEPROM DDR2 SDRAM Package: 60 ball(x4/x8) 133.35 x 30.00 mm form factor RoHS compliant
* * * * * *
ORDERING INFORMATION
Part Name HMP31GP7AFR4C - Y5/S5/S6 Density 8GB Organization 1G X 72 # of DRAMs 36 # of ranks 2 Parity Support O
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1 / Jan. 2009 1
1240pin Registered DDR2 SDRAM DIMMs SPEED GRADE & KEY PARAMETERS
Y5 (DDR2-667) Speed@CL3 Speed@CL4 Speed@CL5 Speed@CL6 CL-tRCD-tRP 400 533 667 5-5-5 S6 (DDR2-800) 533 667 800 6-6-6 S5 (DDR2-800) 400 533 800 5-5-5 Unit Mbps Mbps Mbps Mbps tCK
ADDRESS TABLE
Density Organization
8GB 1G x 72
Ranks
2
SDRAMs
512Mb x 4
# of DRAMs
36
# of row/bank/column Address
15(A0~A14)/3(BA0~BA2)/11(A0~A9,A11)
Refresh Method
8K / 64ms
Rev. 0.1 / Jan. 2009
2
1240pin Registered DDR2 SDRAM DIMMs Input/Output Functional Description
Symbol
CK0
Type
IN
Polarity
Positive Edge Negative Edge Active High
Pin Description
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
CK0
IN
Negative line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
CKE[1:0]
IN
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. Enables the associated DDR2 SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1 On-Die Termination signals. When sampled at the positive rising edge of the clock. RAS,CAS and WE(ALONG WITH S) define the command being entered. Reference voltage for SSTL18 inputs Power supplies for the DDR2 SDRAM output buffers to provide improved noise immunity. For all current DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins.
S[1:0]
IN
Active Low
ODT[1:0] RAS, CAS, WE Vref VDDQ BA[2:0]
IN IN Supply Supply IN
Active High Active Low
-
Selects which DDR2 SDRAM internal bank of Eight is activated. During a Bank Activate command cycle, Address input defines the row address(RA0~RA13) During a Read or Write command cycle, Address input defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke auto precharge operation at the end of the burst read or write cycle. If AP is high., auto precharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge. Data and Check Bit Input/Output pins.
A[9:0],A10/AP A[13:11]
IN
-
DQ[63:0], CB[7:0]
IN
-
DM[8:0]
IN
Active High
DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Power and ground for the DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to VDD/VDDQ planes on these modules.
VDD,VSS
Supply Positive Edge Negative Edge -
DQS[17:0]
IO
Positive line of the differential data strobe for input and output data
DQS[17:0]
IO
Negative line of the differential data strobe for input and output data
SA[2:0]
IN
These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range. This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister may be connected from the SDA bus line to VDDSPD on the system planar to act as a pull up. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from SCL to VDDSPD to act as a pull up on the system board. Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane. EEPROM supply is operable from 1.7V to 3.6V. The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low level (the PLL will remain synchronized with the input clock) Parity bit for the Address and Control bus("1". Odd, "0".Even) Parity error found in the Address and Control bus Used by memory bus analysis tools(unused on memory DIMMs)
SDA
I/O
-
SCL
IN
-
VDDSPD
Supply
RESET
IN
Par_In Err_Out TEST
IN OUT
Rev. 0.1 / Jan. 2009
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1240pin Registered DDR2 SDRAM DIMMs PIN DESCRIPTION
Pin
CK0 CK0 CKE0~CKE1 RAS CAS WE S0,S1 A0~A9,A11~A13 A10/AP BA0, BA1, BA2 SCL SDA SA0~SA2 Par_In Err_Out RESET CB0~CB7
Pin Description
Clock Input, positive line Clock input, negative line Clock Enable Input Row Address Strobe Column Address Strobe Write Enable Chip Select Input Address input Address input/Autoprecharge SDRAM Bank Address Serial Presence Detect(SPD) Clock Input SPD Data Input/Output E2PROM Address Inputs Parity bit for the Address and Control bus Parity error found on the Addre Reset Enable Data Strobe Inputs/Outputs
Pin
ODT[1:0] VDDQ DQ0~DQ63 CB0~CB7 DQS(0~8) DQS(0~8) DM(0~8),DQS(9~17) DQS(9~17) RFU NC TEST VDD VDDQ VSS VREF VDDSPD
Pin Description
On Die Termination Inputs DQs Power Supply Data Input/Output Data check bits Input/Output Data strobes Data strobes, negative line Data Makes/Data strobes Data strobes, negative line Reserved for Future Use No Connect Memory bus test tool (Not Connected and Not Usable on DIMMs) Core Power I/O Power Supply Ground Reference Power Supply Power Supply for SPD
PIN LOCATION
pin #1
Front Side
Pin #64
Pin #65
Pin #120
Pin #121
Back Side
Pin #184
Pin #185
pin #240
Rev. 0.1 / Jan. 2009
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1240pin Registered DDR2 SDRAM DIMMs PIN ASSIGNMENT
Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Name
VREF VSS DQ0 DQ1 VSS DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 VSS RESET NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3 DQS3 VSS DQ26 DQ27
Pin
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Name
VSS CB0 CB1 VSS DQS8 DQS8 VSS CB2 CB3 VSS VDDQ CKE0 VDD BA2,NC NC,Err_Out VDDQ A11 A7 VDD A5 A4 VDDQ A2 VDD Key
Pin
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
Name
DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 NC(TEST) VSS DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7 DQS7 VSS DQ58 DQ59 VSS SDA SCL
Pin
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
Name
VSS DQ4 DQ5 VSS DM0/DQS9 DQS9 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1/DQS10 DQS10 VSS RFU RFU VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2/DQS11 DQS11 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3/DQS12 DQS12 VSS DQ30 DQ31 VSS
Pin
161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184
Name
CB4 CB5 VSS DM8,DQS17 DQS17 VSS CB6 CB7 VSS VDDQ NC,CKE1 VDD A15,NC A14,NC VDDQ A12 A9 VDD A8 A6 VDDQ A3 A1 VDD Key
Pin
201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225
Name
VSS DM4/DQS13 DQS13 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5/DQS14 DQS14 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS RFU RFU VSS DM6/DQS15 NC,DQS15 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7/DQS16 NC,DQS16 VSS DQ62 DQ63 VSS VDDSPD SA0 SA1
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
VSS VSS VDD NC,Err_Out VDD A10/AP BA0 VDDQ WE CAS VDDQ NC, S1 NC, ODT1 VDDQ VSS DQ32
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
CK0 CK0 VDD A0 VDD BA1 VDDQ RAS S0 VDDQ ODT0 A13,NC VDD VSS DQ36 DQ37
226 227 228 229 230 231 232 233 234 235 236 237 238 239 240
NC= No Connect, RFU= Reserved for Future Use.
Note: 1. RESET(Pin 18) is connected to both OE of PLL and Reset of register. 2. NC/Err_out (Pin 55) and NC/Par_In(Pin68) are for optional function to check address and command parity. 3. The Test pin(Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules(DIMMs)
Rev. 0.1 / Jan. 2009
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1240pin Registered DDR2 SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM 8GB(1Gbx72): HMP31GP7AFR4C
VSS RS0 RS1 DQS0 DQS0 DM CS DQS DQS DQ0 DQ1 DQ2 DQ3 DQS1 DQS1 DQ8 DQ9 DQ10 DQ11 DQS2 DQS2 DQ16 DQ17 DQ18 DQ19 DQS3 DQS3 DM CS DQS DQS DQ24 DQ25 DQ26 DQ27 DQS8 DQS8 DM CS DQS DQS CB0 CB1 CB2 CB3 RS0 RS1 DQS4 DQS4 DM CS DQS DQS DQ32 DQ33 DQ34 DQ35 DQS5 DQS5 DQ40 DQ41 DQ42 DQ43 DQS6 DQS6 DQ48 DQ49 DQ50 DQ51 DQS7 DQS7 DM CS DQS DQS DQ56 DQ57 DQ58 DQ59 I/O 0 I/O 1 I/O 2 I/O 3 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS9 DQS9 DM CS DQS DQS DQ4 DQ5 DQ6 DQ7 DQS10 DQS10 DQ12 DQ13 DQ14 DQ15 DQS11 DQS11 DQ20 DQ21 DQ22 DQ23 DQS12 DQS12 DM CS DQS DQS DQ28 DQ29 DQ30 DQ30 DQS17 DQS17 DM CS DQS DQS CB4 CB5 CB6 CB7 I/O 0 I/O 1 I/O 2 I/O 3 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3
D0
D18
D9
D27
Serial PD SCL WP A0 A1 A2 SDA
DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3
DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3
DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3
DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 SA0 SA1 SA2
D1
D19
D10
D28
DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3
DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3
DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3
DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3
VDDSPD VDD/VDDQ VREF VSS
SPD
D0-D35 D0-D35 D0-D35
D2
D20
D11
D29
D3
D21
D12
D30
D8
D26
D17
D35
Signals for Address and Command Parity Function Register Par_In
PARIN PTYERR
Register
DQS13 DQS13 DM CS DQS DQS DQ36 DQ37 DQ38 DQ39 DQS14 DQS14 DQ44 DQ45 DQ46 DQ47 DQS15 DQS15 DQ52 DQ53 DQ54 DQ55 DQS16 DQS16 DM CS DQS DQS DQ60 DQ61 DQ62 DQ63 I/O 0 I/O 1 I/O 2 I/O 3 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 K PARIN PTYERR
Err_Out
D4
D22
D13
D31
o ohm resistor on Err_Out is not populated for non-parity card. The resistors on Par_In,A13,A14,A15,BA2 and the signal line of Err_Out refer to the section: "Register Options for Unused Address input"
DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3
DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3
DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3
DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3
D5
D23
D14
D32
DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3
DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3
DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3
DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3
D6
D24
D15
D33
D7
D25
D16
D34
S0* S1* BA0-BA2*** A0-A15*** RAS CAS WE CKE0 CKE1 ODT0 ODT1 RESET** PCK7** PCK7** 1:2 R E G I S T E R
RST
RS0 -> CS: SDRAMs D0-D17 RS1 -> CS: SDRAMs D18-D35 RBA0-RBA2 -> BA0-BA2: SDRAMs D0-D35 RA0-RA15 -> A0-A15: SDRAMs D0-D35 RRAS -> RAS: SDRAMs D0-D35 RCAS -> CAS: SDRAMs D0-D35 RWE -> WE: SDRAMs D0-D35 RCKE0 -> CKE0-1: SDRAMs D0-D17 RCKE1 -> CKE0-1: SDRAMs D18-D35 RODT0 -> ODT1: SDRAMs D0-D17 RODT1 -> ODT1: SDRAMs D18-D35 CK0 CK0 RESET P L L
OE
PCK0-PCK6, PCK8, PCK9 -> CK: SDRAMs D0-D35 PCK0-PCK6, PCK8, PCK9 -> CK: SDRAMs D0-D35 PCK7 -> CK: Register PCK7 -> CK: Register
Note:
1. DQ-to-I/O wiring may be changed within a nibble. 2. Unless otherwise noted, resistor values are 22 Ohms 5%. 3. RS0 and RS1 alternate between the bottom and surface sides of the DIMM.
*S0 connects to DCS and S1 command to CRS on a pair of Register, S2 connects to DCS and S0 connect to CRS on another pair of Register. ** RESET, PCK7 and PCK7 connect to all Registers. Other signals connect to one pair of four Registers. *** A14-15, BA2 have the optional pull down resistors (100K ohms), which is not indicated here.
Rev. 0.1 / Jan. 2009
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1240pin Registered DDR2 SDRAM DIMMs ABSOLUTE MAXIMUM DC RATINGS
Parameter Voltage on VDD pin relative to Vss Voltage on VDDQ pin relative to Vss Voltage on VDDL pin relative to Vss Voltage on any pin relative to Vss Symbol VDD VDDQ VDDL VIN, VOUT Value - 1.0 ~ 2.3 - 0.5 ~ 2.3 - 0.5 ~ 2.3 - 0.5 ~ 2.3 Unit V V V V Note 1 1 1 1
Operating Conditions and Environmental Parameters
Parameter
DIMM Operating temperature(ambient) Storage Temperature Storage Humidity(without condensation) DIMM Barometric Pressure(operating & storage) DRAM Component Case Temperature Range
Note: 1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating con ditions for extended periods may affect reliability. 2. Up to 9850 ft. 3. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced to tREFI=3.9us. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2.
Symbol
TOPR TSTG HSTG PBAR TCASE
Rating
0 ~ +55 -50 ~ +100 5 to 95 105 to 69 0 ~+95
Units
o o
Notes
C C 1 1 2 3
% K Pascal
oC
DC OPERATING CONDITIONS
Symbol VDD VDDL VDDQ VREF VTT VDDSPD Note: Parameter Supply Voltage Supply Voltage for DLL Supply Voltage for Output Input Reference Voltage Termination Voltage EEPROM Supply Voltage
(SSTL_1.8)
Rating Min. 1.7 1.7 1.7 0.49*VDDQ VREF-0.04 1.7 Typ. 1.8 1.8 1.8 0.50*VDDQ VREF Max. 1.9 1.9 1.9 0.51*VDDQ VREF+0.04 3.6
Units V V V mV V V
Notes 1 1,2 1,2 3,4 5
1. Min. Type. and Max. values increase by 100mV for C3(DDR2-533 3-3-3) speed option. 2. VDDQ tracks with VDD,VDDL tracks with VDD. AC parameters are measured with VDD,VDDQ and VDD. 3. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 4. Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc). 5. VTT of transmitting device must track VREF of receiving device.
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1240pin Registered DDR2 SDRAM DIMMs INPUT DC LOGIC LEVEL
Parameter dc Input logic HIGH dc Input logic LOW Symbol VIH(DC) VIL(DC) Min VREF + 0.125 -0.30 Max VDDQ + 0.3 VREF - 0.125 Unit V V Note
INPUT AC LOGIC LEVEL
Parameter ac Input logic HIGH ac Input logic LOW Symbol VIH(AC) VIL(AC) DDR2 667/800 Min VREF + 0.200 Max VREF - 0.200 Unit V V Notes
AC INPUT TEST CONDITIONS
Symbol VREF VSWING(MAX) SLEW Note:
1. 2. 3. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. The input signal minimum slew rate is to be maintained over the range from VREF max to VIH(ac) min for rising edges and the range from VREF min to VIL(ac) max for falling edges as shown in the below figure. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions.
Condition Input reference voltage Input signal maximum peak to peak swing Input signal minimum slew rate
Value 0.5 * VDDQ 1.0 1.0
Units V V V/ns
Notes 1 1 2, 3
Start of Falling Edge Input Timing
Start of Rising Edge Input Timing
VSWING(MAX)
VDDQ VIH(ac) min VIH(dc) min VREF VIL(dc) max VIL(ac) max VSS
VIH(ac) min - VREF
TF
Falling Slew = VREF - VIL(ac) max
TR TF
Rising Slew =
TR
< Figure: AC Input Test Signal Waveform >
Rev. 0.1 / Jan. 2009
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1240pin Registered DDR2 SDRAM DIMMs
Differential Input AC logic Level
Symbol VID (ac) VIX (ac) Note:
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS and UDQS. 2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to VIH(DC) - VIL(DC).
Parameter ac differential input voltage ac differential cross point voltage
Min. 0.5 0.5 * VDDQ - 0.175
Max. VDDQ + 0.6 0.5 * VDDQ + 0.175
Units V V
Note 1 2
VDDQ VTR VID VCP VSSQ
< Differential signal levels >
Note:
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V IH(AC) - VIL(AC). 2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ. VIX(AC) indicates the voltage at which differential input signals must cross. Crossing point
VIX or VOX
DIFFERENTIAL AC OUTPUT PARAMETERS
Symbol VOX (ac) Note:
1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ. VOX(AC) indicates the voltage at which differential output signals must cross.
Parameter ac differential crosspoint voltage
Min. 0.5 * VDDQ - 0.125
Max. 0.5 * VDDQ + 0.125
Units V
Note 1
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1240pin Registered DDR2 SDRAM DIMMs
OUTPUT BUFFER LEVELS
OUTPUT AC TEST CONDITIONS
Symbol VOTR Note:
1. The VDDQ of the device under test is referenced.
Parameter Output Timing Measurement Reference Level
SSTL_18 0.5 * VDDQ
Units V
Notes 1
OUTPUT DC CURRENT DRIVE
Symbol IOH(dc) IOL(dc) Note:
1.VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ - 280 mV. 2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV. 3. The dc value of VREF applied to the receiving device is set to VTT 4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point along a 21 ohm load line to define a convenient driver current for measurement.
Parameter Output Minimum Source DC Current Output Minimum Sink DC Current
SSTl_18 - 13.4 13.4
Units mA mA
Notes 1, 3, 4 2, 3, 4
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1240pin Registered DDR2 SDRAM DIMMs
PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25C)
8GB: HMP31GP7AFR4C
Pin CK0, /CK0 CKE, ODT /CS Address, /RAS, /CAS, /WE DQ, DM, DQS, /DQS Symbol CCK CI1 CI2 CI3 CIO Min TBD TBD TBD TBD TBD Max TBD TBD TBD TBD TBD Unit pF pF pF pF pF
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1240pin Registered DDR2 SDRAM DIMMs
IDD SPECIFICATIONS (TCASE: 0 to 95oC)
8GB, 1G x 72 Registered DIMM: HMP31GP7AFR4C
Symbol
IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P(F) IDD3P(S) IDD3N IDD4W IDD4R IDD5B IDD6 IDD7
Y5 (DDR2 667@CL5)
3170 3350 1082 2270 2450 1910 1298 3170 5150 4880 5310 990 6590
S6 (DDR2 800@CL6)
3350 3530 1082 2450 2630 1910 1298 3530 5960 5600 5580 990 7130
Unit
mA mA mA mA mA mA mA mA mA mA mA mA mA
Note
1
Note: 1. IDD6 current values are guaranteed up to Tcase of 85Cmax.
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1240pin Registered DDR2 SDRAM DIMMs
IDD Measurement Conditions
Symbol IDD0 Conditions
Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD);CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus inputs are SWITCHING Operating one bank active-read-precharge current; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current;All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0 Slow PDN Exit MRS(12) = 1
Units
mA
IDD1
mA
IDD2P IDD2Q IDD2N
mA
mA
mA mA mA
IDD3P
IDD3N
Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING. IDD6 current values are guaranteed up to Tcase of 85 max. Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for detailed timing conditions
mA
IDD4W
mA
IDD4R
mA
IDD5B
mA
IDD6
mA
IDD7
mA
Note:
1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD LOW is defined as Vin VILAC (max) HIGH is defined as Vin VIHAC (min) STABLE is defined as inputs stable at a HIGH or LOW level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes
Rev. 0.1 / Jan. 2009
13
1240pin Registered DDR2 SDRAM DIMMs
Electrical Characteristics & AC Timings
Speed Bins and CL,tRCD,tRP,tRC and tRAS for Corresponding Bin
Speed
Bin(CL-tRCD-tRP) Parameter CAS Latency tRCD tRP tRC tRAS
DDR2-800 (S5)
5-5-5 min 5 12.5 12.5 57.5 45
DDR2-667 (Y5)
5-5-5 min 5 15 15 60 45
Unit
ns ns ns ns ns
Rev. 0.1 / Jan. 2009
14
1240pin Registered DDR2 SDRAM DIMMs AC Timing Parameters by Speed Grade (DDR2-667 & DDR2-800)
Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width CK half period Clock cycle time, CL=x DQ and DM input setup time (differential strobe) DQ and DM input hold time (differential strobe) Control & Address input pulse width for each input DQ and DM input pulse width for each input Data-out high-impedance time from CK/CK DQS low-impedance time from CK/CK DQ low-impedance time from CK/CK DQS-DQ skew for DQS and associated DQ signals DQ hold skew factor DQ/DQS output hold time from DQS First DQS latching transition to associated clock edge DQS input high pulse width DQS input low pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK Mode register set command cycle time Write preamble Write postamble Auto-Refresh to Active/Auto-Refresh command period Row Active to Row Active Delay for 1KB page size Address and control input setup time Address and control input hold time Read preamble Read postamble Activate to precharge command Active to active command period for 1KB page size products Row Active to Row Active Delay for 2KB page size Four Active Window for 1KB page size products Four Activate Window for 2KB page size CAS to CAS command delay Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal read to precharge command delay Symbol tAC tDQSCK tCH tCL tHP tCK tDS tDH tIPW tDIPW tHZ tLZ(DQS) tLZ(DQ) tDQSQ tQHS tQH tDQSS tDQSH tDQSL tDSS tDSH tMRD tWPRE tWPST tRFC tRRD tIS tIH tRPRE tRPST tRAS tRRD tRRD tFAW tFAW tCCD tWR tDAL tWTR tRTP DDR2-667 min -450 -400 0.45 0.45 min(tCL, tCH) 3000 100 175 0.6 0.35 tAC min 2*tAC min tHP - tQHS - 0.25 0.35 0.35 0.2 0.2 2 0.35 0.4 127.5 7.5 200 275 0.9 0.4 45 7.5 10 37.5 50 2 15 WR+tRP 7.5 7.5 max +450 +400 0.55 0.55 8000 tAC max tAC max tAC max 240 340 + 0.25 0.6 1.1 0.6 70000 min -400 -350 0.45 0.45 min(tCL, tCH) 2500 50 125 0.6 0.35 tAC min 2*tAC min tHP - tQHS - 0.25 0.35 0.35 0.2 0.2 2 0.35 0.4 127.5 7.5 175 250 0.9 0.4 45 7.5 10 35 50 2 15 WR+tRP 7.5 7.5 tAC max tAC max tAC max 200 300 + 0.25 0.6 1.1 0.6 70000 DDR2-800 max +400 +350 0.55 0.55 Unit ps ps tCK tCK ps ps ps ps tCK tCK ps ps ps ps ps ps tCK tCK tCK tCK tCK tCK tCK tCK ns ns ps ps tCK tCK ns ns ns ns ns tCK ns tCK ns ns 1 1 Note
Rev. 0.1 / Jan. 2009
15
1240pin Registered DDR2 SDRAM DIMMs
Parameter Exit self refresh to a non-read command Exit self refresh to a read command Exit precharge power down to any non-read command Exit active power down to read command Exit active power down to read command (Slow exit, Lower power) CKE minimum pulse width (high and low pulse width) ODT turn-on delay ODT turn-on ODT turn-on(Power-Down mode) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down mode) ODT to power down entry latency ODT power down exit latency OCD drive mode output delay Minimum time clocks remains ON after CKE asynchronously drops LOW Average periodic Refresh Interval
Symbol tXSNR tXSRD tXP tXARD tXARDS tCKE tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD tOIT tDelay tREFI tREFI
DDR2-667 min tRFC + 10 200 2 2 7 - AL 3 2 tAC(min) tAC(min)+2 2.5 tAC(min) tAC(min) +2 3 8 0 tIS+tCK+tIH 7.8 3.9 12 2 tAC(max) +0.7 2tCK+ tAC(max)+1 2.5 tAC(max)+ 0.6 2.5tCK+ tAC(max)+1 max min
DDR2-800 max tRFC + 10 200 2 2 8 - AL 3 2 tAC(min) tAC(min) +2 2.5 tAC(min) tAC(min) +2 3 8 0 tIS+tCK +tIH 7.8 3.9 12 2 tAC(max) +0.7 2tCK+ tAC(max)+1 2.5 tAC(max) +0.6 2.5tCK+ tAC(max)+1
Unit ns tCK tCK tCK tCK tCK tCK ns ns tCK ns ns tCK tCK ns ns us us
Note
2 3
Note: 1. For details and notes, please refer to the relevant HYNIX component datasheet H5PS2G[4,8]3AFR. C 2. 0C TCASE C TCASE C
Rev. 0.1 / Jan. 2009
16
1240pin Registered DDR2 SDRAM DIMMs PACKAGE OUTLINE 1Gx72 (2 ranks) - HMP31GP7AFR4C Front
2X 3.00MIN
PLL
4X FULL R 17.80 30.00 10.00 2X 0.10
4X 4.0
0.1
2X 2.3 0.1 5.175
Register
2X R1.00
63.0
DETAIL-A
5.0
128.95 133.35
DETAIL-B
55.0
Back
Register
Detail of Contacts A
0.20
Detail of Contacts B
2.50
0.15
Side
4.00max
0.35 0.05
2.50
3.0
1.0
0.8
0.05
1.50
0.10
0.3 ~ 1.0
3.80
5.00
1.27
0.10
Note) All dimensions are typical unless otherwise stated.
Millimeters Inches
Rev. 0.1 / Jan. 2009
17
1240pin Registered DDR2 SDRAM DIMMs REVISION HISTORY
Revision 0.1 History Initial data sheet released Date Jan. 2009
Rev. 0.1 / Jan. 2009
18

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